It is known to make electric interconnects or electric contact pick-ups in a substrate by forming vias, i.e. holes or cavities, in that substrate, then by metalizing said vias, i.e. filling them with an electrically conducting material, such as metal.
Such metallization of the vias formed in a substrate can be obtained by using traditional vacuum deposition methods, e.g. PVD (physical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), electrolysis, etc. These methods are suitable for metalizing vias with small diameters, for example smaller than about 100 μm, and small depths.
However, these methods become unsuitable when one wishes to metalize vias with larger depths, for example in the case of through vias formed in the entire thickness of a semiconducting substrate such as silicon, the standard thickness of which is equal to about 720 μm, and even for vias having patterns with large dimensions, i.e. having a diameter greater than or equal to about 200 μm, due to the extremely long implementation times needed, and therefore the cost of performing such metallizations.
In order to reduce this cost, it is also known to metalize vias using serigraphy: the electrically conducting material is arranged on the substrate in the form of a paste then, via a doctor blade, said paste is introduced into the vias.
However, such metallization by serigraphy poses problems in the cases of so-called “blind” vias, i.e. non-through vias that emerge on a single face of the substrate and have a bottom wall formed either in the substrate or by a second substrate made integral with the first substrate. The most frequent flaws then encountered are the capture of air bubbles in the vias, under the electrically conducting material, and/or partial filling of the vias preventing picking up of the electric contacts formed by the vias on the side of the bottom walls of the vias.
To offset these problems, document JP 2002/144523 A proposes metalizing vias by carrying out vacuum serigraphy. However, there are many drawbacks related to carrying out such vacuum serigraphy:
the modifications that must be made to the serigraphy equipment to perform such vacuum serigraphy are very expensive,
the time necessary to place the substrate under vacuum before proceeding with the serigraphy is significant,
the serigraphy material used to metalize the vias must be compatible with placement under vacuum, which requires the use of a polymer/metal composite as metallization material,
the quality of the electric interconnect obtained for example between the serigraphed metallization material and the electrically conducting walls of the via is random.